
Lattice USB ISP Download Cable Jtag SPI Programmer for FPGA CPLD
Lattice USB ISP Download Cable Jtag SPI Programmer for FPGA CPLD
Multipurpose ISP-Header01 Adapter Pinout Information
The PCB end of the adapter is composed of 48 pins, dual in line layout. Only the last 5 pins of each column of pins is used. So, it is just a 10 pin header.
Here is the pin mapping layout:
Pin#1 --> Brown
Pin#2 --> Orange
Pin#3 --> Green
Pin#4 --> Purple
Pin#5 --> White
Pin#6 --> Black
Pin#7 --> Grey
Pin#8 --> Blue
Pin#9 --> Yellow
Pin#10 -->Red
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Lattice USB ISP Download Cable Jtag SPI Programmer for FPGA CPLD
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